An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording-Reference-Cited by-同舟云学术

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An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Published:2013-11 Issue:11 Volume:21 Page:2034-2044
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chaturvedi Vikram,Anand Tejasvi,Amrutur Bharadwaj

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6606858/06425797.pdf?arnumber=6425797

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Low-Power Fully Differential Level-Crossing ADC Based on Single-Reference Comparator for Wireless Medical Implantable Devices;Journal of Circuits, Systems and Computers;2024-03-26

2. A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants;Electronics;2021-03-03

3. A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications;IET Circuits, Devices & Systems;2021-01-12

4. Reduced switching mode for SAR ADCs: analysis and design of SAR A‐to‐D algorithm with periodic standby mode circuit components;IET Circuits, Devices & Systems;2020-07-20

5. Resolution-independent fully differential SCI-based SAR ADC architecture using six unit capacitors;Sādhanā;2020-07-20

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