Write Disturbance Modeling and Testing for MRAM-Reference-Cited by-同舟云学术

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Write Disturbance Modeling and Testing for MRAM

Published:2008-03 Issue:3 Volume:16 Page:277-288
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Su Chin-Lung,Tsai Chih-Wea,Wu Cheng-Wen,Hung Chien-Chung,Chen Young-Shying,Wang Ding-Yeong,Lee Yuan-Jen,Kao Ming-Jer

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/4453948/04453958.pdf?arnumber=4453958

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs;2022 IEEE International Test Conference (ITC);2022-09

2. Experimental Study of Adversarial Magnetic Field Exposure Attacks on Toggle MRAM Chips;IEEE Transactions on Electron Devices;2022-03

3. A Survey of Test and Reliability Solutions for Magnetic Random Access Memories;Proceedings of the IEEE;2021-02

4. BIST Architecture for Magnetic Memories;Mathematical Problems of Computer Science;2020-12-25

5. Challenges and Solutions in Emerging Memory Testing;IEEE Transactions on Emerging Topics in Computing;2019-07-01

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