A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation-Reference-Cited by-同舟云学术

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A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation

Published:2018-10 Issue:10 Volume:26 Page:2170-2174
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Jo Youngwoo^ORCID,Kim Hyojun,Cho Seonghwan^ORCID

Funder

National Research Foundation of Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8472222/08396274.pdf?arnumber=8396274

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A Single-Event-Transient Hardened Phase Locked Loop for Clock and Data Recovery;Chinese Journal of Electronics;2024-03

3. An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

4. A-236.5dB Jitter-FoM Dual-Path RO-PLL With Improved Supply Sensitivity;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

5. A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-02

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