Fault-Duration And-Location Aware CED Technique With Runtime Adaptability-Reference-Cited by-同舟云学术

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Fault-Duration And-Location Aware CED Technique With Runtime Adaptability

Published:2014-03 Issue:3 Volume:22 Page:507-515
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Liu Yu,Wu Kaijie

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/6746074/06494331.pdf?arnumber=6494331

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection;Electronics;2018-10-17

2. On Probability of Detection Lossless Concurrent Error Detection Based on Implications;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017

3. Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components;2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2016-07

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