Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis
Author:
Affiliation:
1. Department of Computer Science, University of California at San Diego, La Jolla, CA, USA
2. Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA
Funder
NSF
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
https://ieeexplore.ieee.org/ielam/92/9836323/9774927-aam.pdf
Reference31 articles.
1. Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes
2. PROBE2.0: A Systematic Framework for Routability Assessment from Technology to Design in Advanced Nodes
3. Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning
4. SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes
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1. Fast Design Technology Co-Optimization Framework for Emerging Technology with Hierarchical Graph Embedding;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
3. Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies;Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding;2023-11-02
4. AI/ML algorithms and applications in VLSI design and technology;Integration;2023-11
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