Single Cycle Access Structure for Logic Test
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx5/92/6178142/05753986.pdf?arnumber=5753986
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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2. An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- and Random-Access-Scan (RAS);2019 22nd Euromicro Conference on Digital System Design (DSD);2019-08
3. An improved low transition test pattern generator for low power applications;Design Automation for Embedded Systems;2017-09-27
4. Reducing Test Power and Improving Test Effectiveness for Logic BIST;JSTS:Journal of Semiconductor Technology and Science;2014-10-30
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