A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation-Reference-Cited by-同舟云学术

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A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation

Published:2017-04 Issue:4 Volume:25 Page:1320-1328
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Meribout Mahmoud^ORCID,Teniou Samir

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7882729/07827012.pdf?arnumber=7827012

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