0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS
Author:
Affiliation:
1. Center for Advanced Studies in Electronics Science and Technology, University of Hyderabad, Hyderabad, Telangana, India
2. School of Electrical Sciences, Indian Institute of Technology Bhubaneswar, Bhubaneswar, Odisha, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/10164658/10120659.pdf?arnumber=10120659
Reference29 articles.
1. A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End
2. A −40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS
3. Analysis and design of N-path RF bandstop filters using Walsh-function-based sequence mixing;agrawal;IEEE Trans Microw Theory Techn,2018
4. A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS
5. Subsampling Architecture for Low Power Receivers
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2. A 0.4–1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023
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