Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications-Reference-Cited by-同舟云学术

Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications

Published:2023-01 Issue:1 Volume:31 Page:29-42
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Lopez Davila Henry¹^ORCID,Wu Tsung-Han²^ORCID,Jou Shyh-Jye Jerry²^ORCID,Chen Sau-Gee²,Tsai Pei-Yun³^ORCID

Affiliation:

1. EECS International Graduate Program, National Chiao Tung University, Hsinchu, Taiwan

2. Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

3. Electrical Engineering Department, National Central University, Taoyuan, Taiwan

Funder

Mediatek Inc

Taiwan Ministry of Science and Technology, Taiwan Semiconductor Research Institute (TSRI);

University Shuttle Program of Taiwan Semiconductor Manufacturing Company (TSMC) and Synopsys

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

Reference38 articles.

5. 3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm;onizawa;Proc 50th Midwest Symp Circuits Syst,2007

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