Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications-Reference-Cited by-同舟云学术

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Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications

Published:2015-09 Issue:9 Volume:23 Page:1969-1972
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Azarderakhsh Reza,Kermani Mehran Mozaffari,Bayat-Sarmadi Siavash,Lee Chiou-Yng

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7217857/06891386.pdf?arnumber=6891386

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-performance unified modular multiplication algorithm and hardware architecture over G(2m);Integration;2024-05

2. Design of an S-ECIES Cryptoprocessor Using Gaussian Normal Bases Over GF(2 m );IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-04

3. Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-09

4. Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials;IEEE Transactions on Multi-Scale Computing Systems;2018-10-01

5. Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over $\textit{GF}(2^{m})$ ;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-08

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