Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator-Reference-Cited by-同舟云学术

Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator

Published:2022-03 Issue:3 Volume:30 Page:303-314
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Khalil Kasem¹^ORCID,Eldash Omar²,Kumar Ashok²^ORCID,Bayoumi Magdy³^ORCID

Affiliation:

1. School of Engineering and Applied Sciences, Western Kentucky University, Bowling Green, KY, USA

2. Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA, USA

3. Department of Electrical and Computer Engineering, University of Louisiana at Lafayette, Lafayette, LA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

Reference49 articles.

1. Image recognition algorithm of convolutional neural networks based on matrix 2-norm pooling;ping;Journal of Graphics,2016

2. Multipartite pooling for deep convolutional neural networks;shahriari;arXiv 1710 07435,2017

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