On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs-Reference-Cited by-同舟云学术

On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs

Published:2023-10 Issue:10 Volume:31 Page:1603-1613
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Murali Gauthaman¹^ORCID,Iyer Aditya¹^ORCID,Zhu Lingjun¹^ORCID,Tong Jianming¹^ORCID,Martínez Francisco Muñoz²^ORCID,Srinivasa Srivatsa Rangachar³,Karnik Tanay¹^ORCID,Krishna Tushar¹^ORCID,Lim Sung Kyu¹

Affiliation:

1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

2. Departamento de Ingeniería y Tecnología de Computadores, Facultad de Informática, Universidad de Murcia, Campus Espinardo, Murcia, Spain

3. Intel Corporation, Hillsboro, OR, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/10261320/10221779.pdf?arnumber=10221779

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4. An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks

5. Spring Hill (NNP-I 1000) Intel’s data center inference chip;wechsler;Proc IEEE Hot Chips 31 Symp (HCS),2019

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