Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond-Reference-Cited by-同舟云学术

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

Published:2017-05 Issue:5 Volume:25 Page:1669-1680
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Huynh-Bao Trong,Ryckaert Julien,Tokei Zsolt,Mercha Abdelkarim,Verkest Diederik,Thean Aaron Voon-Yew,Wambacq Piet

Funder

IMEC's (sub-)10nm CMOS Industrial Affiliation Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

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