A Reusable and Efficient Architecture for QC-LDPC Encoder With Less Expansion Factors
Author:
Affiliation:
1. Beijing Key Laboratory of Network System Architecture and Convergence, Beijing Laboratory of Advanced Information Networks, Beijing University of Posts and Telecommunications, Beijing, China
Funder
Beijing Natural Science Foundation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/10328903/10286376.pdf?arnumber=10286376
Reference32 articles.
1. A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio
2. Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders
3. Efficient helicopter−satellite communication scheme based on check-hybrid LDPC coding
4. A Flexible Hardware Encoder for Low-Density Parity-Check Codes
5. FPGA Design and Implementation of DVB-S2/S2X LDPC Encoder
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