Author:
Archana H R,Sanjana T,Bhavana H T,Sunil S V
Cited by
4 articles.
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1. Design of Low Power ALU for RISC-VISA;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18
2. Design and Implementation of Optimized Based 32-Bit Arithmetic and Logical Unit;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01
3. A High-Level Synthesis Approach for a RISC-V RV32I-Based System on Chip and Its FPGA Implementation;The 10th International Electronic Conference on Sensors and Applications;2023-11-15
4. Verification and Validation of 64-Bit Processor Memory System;Proceedings of Third International Conference on Sustainable Expert Systems;2023