Author:
Kumar Arun,Ansari Asif,Srivastava Ayush,Suneja Kriti
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of a 4-Bit 4-Operand Adder Using Verilog: An Abstraction Analysis;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
2. FPGA-based Pipelined LSTM accelerator with Approximate matrix multiplication technique;2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT);2021-12-10