Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5290879/5290880/05290932.pdf?arnumber=5290932
Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Scalable, high-speed on-chip-based NDN name forwarding using FPGA;Proceedings of the 20th International Conference on Distributed Computing and Networking;2019-01-04
2. Application specific cache design using STT-RAM based block-RAM for FPGA-based soft processors;IEICE Electronics Express;2018
3. Compressing IP Forwarding Tables with Small Bounded Update Time;Computer Networks;2016-09
4. Pipelined hierarchical architecture for high performance packet classification;Computer Networks;2016-07
5. A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units;IEICE Transactions on Information and Systems;2015
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