Author:
Morris Gerald,Prasanna Viktor,Anderson Richard
Cited by
13 articles.
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1. Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays;ACM Transactions on Reconfigurable Technology and Systems;2022-06-30
2. Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System;Electronics;2020-09-10
3. Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLS;Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2019-02-20
4. FASTCF;Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2018-02-15
5. Scale-out acceleration for machine learning;Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture;2017-10-14