SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation
Author:
Affiliation:
1. Korea University,Department of Electrical Engineering,Seoul,Korea
Funder
National Research Foundation of Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10031262/10031265/10031591.pdf?arnumber=10031591
Reference4 articles.
1. A replica technique for wordline and sense control in low-power SRAM's
2. A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
3. A low-power, high-performance, 1024-point FFT processor
4. A 180-mV subthreshold FFT processor using a minimum energy design methodology
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