PROG: Per-Row Output Generator for BOST
Author:
Affiliation:
1. Yonsei University,Dept. of Electrical and Electronic Engineering,Seoul,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10031262/10031265/10031319.pdf?arnumber=10031319
Reference5 articles.
1. Reduced-Pin-Count BOST for Test-Cost Reduction
2. Fail Memory Configuration Set for RA Estimation
3. At-speed Test of High-Speed DUT Using Built-Off Test Interface
4. Stretching the limits of FPGA SerDes for enhanced ATE performance
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