A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE
Author:
Affiliation:
1. Seoul National University,Dept. of Electrical and Computer Engineering,Seoul,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10031262/10031265/10031547.pdf?arnumber=10031547
Reference5 articles.
1. 19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation
2. A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation
3. A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
4. Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture
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