Determining PCIe5 Jitter Margin using SIPI Co-Sim
Author:
Affiliation:
1. Sze Lin Mak and Chee Hoong Mah Client System Architecture & Engineering Intel Corporation,Penang,Malaysia
2. Assembly Test Technology Development Intel Corporation,Penang,Malaysia
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10031262/10031265/10031312.pdf?arnumber=10031312
Reference7 articles.
1. Power Delivery Network simulation methodology including Integrated Circuit behavior
2. Analysis and Calculation of Transfer Functions Relating Power Supply Noise to Jitter Based on Output Buffer of LVSTL Interface
3. Signal/Power Integrity Co-Simulation of DDR3 Memory Module;chao-kai;IEEE International Conference on Computational Electromagnetics (ICCEM) 2018,0
4. An enhanced high-precision and time-saving jitter transfer measurement
5. Jitter transfer function model and VLSI jitter filter circuits
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