Design and Implementation of a Low Power Time-to-Digital Converter for Pixel Application

Author:

Pass Mohammad Hassan1,Sayedi Sayed Masoud1,Mehr Seyed Amir Reza Ahmadi1

Affiliation:

1. Isfahan University of Technology,Department of Electrical and Computer Engineering,Isfahan,Iran,84156-83111

Publisher

IEEE

Reference12 articles.

1. CMOS imager with 1024 SPADs and TDCs for single-photon timing and 3-D time-of-flight;federica;IEEE Journal of Selected Topics in Quantum Electronics,2014

2. Design and Characterization of a 43.2-ps and PVT-Resilient TDC for Single-Photon Imaging Arrays

3. A 30-frames/s, $252\times144 $ SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming;chao;IEEE Journal of Solid-State Circuits,2018

4. A 32× 128 SPAD-257 TDC receiver IC for pulsed TOF solid-state 3-D imaging;sahba;IEEE Journal of Solid-State Circuits,2020

5. A 30-frames/s, $252\times144$ SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Low-Power Cyclic Vernier Time-to-Digital Converter for In Pixel Applications;2023 31st International Conference on Electrical Engineering (ICEE);2023-05-09

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