Hybrid Rule-based and Machine Learning System for Assertion Generation from Natural Language Specifications
Author:
Affiliation:
1. Virginia Tech Blacksburg,Department of Electrical and Computer Engineering,Virginia,USA,24061
Funder
NSF
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9978942/9978943/09979024.pdf?arnumber=9979024
Reference10 articles.
1. Chatbot-based assertion generation from natural language specifications
2. Automatic Assertion Generation from Natural Language Specifications Using Subtree Analysis
3. Evaluating Large Language Models Trained on Code;chen;CoRR,2021
4. SpecToSVA: Circuit Specification Document to SystemVerilog Assertion Translation;parthasarathy;2021 Second Document Intelligence Workshop at KDD,0
5. EASE: Enabling Hardware Assertion Synthesis from English
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1. Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect;ACM Transactions on Design Automation of Electronic Systems;2024-06-21
2. FormalEval: A Method for Automatic Evaluation of Code Generation via Large Language Models;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
3. Natural2CTL: A Dataset for Natural Language Requirements and Their CTL Formal Equivalents;Lecture Notes in Computer Science;2024
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