Dead Time Optimization for Synchronous Switching of SiC MOSFETs Considering Nonlinear Gate Capacitance
Author:
Affiliation:
1. School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan, China
2. Hubei Jiufengshan Laboratory, Wuhan, China
Funder
National Natural Science Foundation of China
Hubei Jiufengshan Laboratory
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/63/10067244/10032647.pdf?arnumber=10032647
Reference12 articles.
1. Nonlinear Capacitance Model of SiC MOSFET Considering Envelope of Switching Trajectory
2. Accuracy of Three Interterminal Capacitance Models for SiC Power MOSFETs Under Fast Switching
3. Characterization of Wide Bandgap Power Semiconductor Devices
4. Characterization and modeling of high-switching-speed behavior of SiC active devices;chen,2009
5. A High-Efficiency Dynamic Inverter Dead-Time Adjustment Method Based on an Improved GaN HEMTs Switching Model
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