Switching Loss Optimization for a Pulsewidth Modulation Strategy With Reduced CMV and Improved Output Harmonic Distortion for a Three-Level NPC Converter-Reference-Cited by-同舟云学术

Switching Loss Optimization for a Pulsewidth Modulation Strategy With Reduced CMV and Improved Output Harmonic Distortion for a Three-Level NPC Converter

Published:2022-10 Issue:10 Volume:37 Page:12118-12133
ISSN:0885-8993
Container-title:IEEE Transactions on Power Electronics
language:
Short-container-title:IEEE Trans. Power Electron.

Author:

Pham Khoa Dang¹^ORCID,Nguyen Nho-Van¹^ORCID

Affiliation:

1. Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam

Funder

National Foundation for Science and Technology Development

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/63/9803836/09779072.pdf?arnumber=9779072

Reference30 articles.

1. Hybrid PWM update method for time delay compensation in current control loop;moon,2017

2. PWM Strategy to Alleviate Common-Mode Voltage with Minimized Output Harmonic Distortion for Five-Level Cascaded H-Bridge Converters

3. A Double Modulation Wave CBPWM Strategy Providing Neutral-Point Voltage Oscillation Elimination and CMV Reduction for Three-Level NPC Inverters

4. A Comprehensive Study of Common Mode Voltage Reduction and Neutral Point Potential Balance for a Back-to-Back Three-Level NPC Converter

5. An Improved Simplified PWM for Three-Level Neutral Point Clamped Inverter Based on Two-Level Common-Mode Voltage Reduction PWM

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