An Adaptive Lockstep Architecture for Mixed-Criticality Systems

Author:

Kempf Fabian,Hartmann Thomas,Baehr Steffen,Becker Juergen

Publisher

IEEE

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Low-Stall Methodology for an Interleaved Processor State Replication;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

2. Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space;ACM Transactions on Cyber-Physical Systems;2023-11-30

3. Adaptive Lock-Step System for Resilient Multiprocessing Architectures;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

4. The TETRISC SoC—A resilient quad-core system based on the ResiliCell approach;Microelectronics Reliability;2023-09

5. Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems;2023 12th Mediterranean Conference on Embedded Computing (MECO);2023-06-06

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