Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck

Author:

Fettweis G.,Meyr H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 71 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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4. Design of a low power and high-speed Viterbi decoder using T-algorithm with normalization;2021 International Conference on Advances in Computing and Communications (ICACC);2021-10-21

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