Demonstration of an 8-Bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells

Author:

Kawaguchi Takahiro,Tanaka Masamitsu,Takagi Kazuyoshi,Takagi Naofumi

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Algebraic and Boolean Methods for SFQ Superconducting Circuits;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

2. Towards Multiphase Clocking in Single-Flux Quantum Systems;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. Superconductive Electronics: A 25-Year Review [Feature];IEEE Circuits and Systems Magazine;2024

4. Synthesis of SFQ Circuits with Compound Gates;2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC);2023-10-16

5. Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits;IEEE Transactions on Applied Superconductivity;2023-08

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