A four-quadrant CMOS analog multiplier for analog neural networks
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx1/4/7239/00293124.pdf?arnumber=293124
Cited by 45 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Process, Bias, and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-01
2. Conjugate Adder Net (CAddNet) - a Space-Efficient Approximate CNN;2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW);2022-06
3. A New Low Voltage Current Mode Analog Multiplier/Divider Circuit Based on FGMOS Translinear Loop;Iranian Journal of Science and Technology, Transactions of Electrical Engineering;2022-01-25
4. Novel architecture of four quadrant analog multiplier/divider circuit employing single CFOA;Analog Integrated Circuits and Signal Processing;2021-07-15
5. Four-Quadrant CMOS Analog Current Multiplier Using Frequency Compensation and 1.5 V Supply;Arabian Journal for Science and Engineering;2021-04-11
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