1. Implementation of a Turbo-Like Error Correction Decoder on a GPU;2024 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO);2024-07-01
2. On Progressive Edge Growth Parity Check Matrix Generation for NB-LDPC Codes in HF Communications;2024 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO);2024-07-01
3. Implementation of M-CpFSK Signal Reception Using ARM Processor with GPU and SDR Receiver;2023 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO;2023-06-28
4. Signal-Code Constructions for Wideband Signals Based on M-Cpfsk and Non-Binary Error-Correcting Codes;2023 Systems of Signals Generating and Processing in the Field of on Board Communications;2023-03-14
5. Implementation of a Multi-Channel Demodulator of Discrete-Frequency Signals Using DDC on a GPU;2022 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO);2022-06-29