A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces
Author:
Affiliation:
1. Korea University,Seoul,Korea
2. Incheon National University,Incheon,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731740.pdf?arnumber=9731740
Reference6 articles.
1. A low-PDP and low-area repeater using passive CTLE for on-chip interconnects
2. Current-Mode Transceiver for Silicon Interposer Channel
3. 6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels
4. A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer
5. A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line
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