A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1 dB FoM Using a Proportionally Divided Charge Pump
Author:
Affiliation:
1. University of California,Berkeley,CA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731760.pdf?arnumber=9731760
Reference7 articles.
1. An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO
2. A 24–31 GHz Reference Oversampling ADPLL Achieving FoMjitter−N of -269.3 dB
3. 19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter;hussein;ISSCC,2017
4. A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation
5. 9.7 a self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 1 0.1-to-12.4GHz, -246.6dB-FoM, fractional-N subsampling PLL;markulic;ISSCC,2016
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1. A 28.8-to-43.2 GHz 79.8 fsrms Jitter and −78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration;IEEE Transactions on Microwave Theory and Techniques;2024-05
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