Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC
Author:
Affiliation:
1. Samsung Electronics,Hwaseong,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731111.pdf?arnumber=9731111
Reference6 articles.
1. A 0.4-to-1V 1MHz-to-2GHz switched-capacitor adiabatic clock driver achieving 55.6% clock power reduction;loai;ISSCC,2017
2. 19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System
3. A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU;kim;ISSCC,2020
4. Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor;lee;Design Automation Conference 2021,0
5. A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache
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1. Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC;IEEE Journal of Solid-State Circuits;2023-01
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