A 57-64 GHz Two-Way Parallel-Combined Power Amplifier with 16.6 dBm Psat and 23.6% Peak PAE in 40nm Bulk CMOS
Author:
Affiliation:
1. Fudan University,State Key Laboratory of ASIC & System,Shanghai,China
2. National Integrated Circuit Innovation Center,Shanghai,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9882303/9882341/09882419.pdf?arnumber=9882419
Reference7 articles.
1. A Wideband, Dual-Path, Millimeter-Wave Power Amplifier With 20 dBm Output Power and PAE Above 15% in 130 nm SiGe-BiCMOS
2. A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS
3. A Coupler-Based Differential Doherty Power Amplifier with Built-In Baluns for High Mm-Wave Linear-Yet-Efficient Gbit/s Amplifications
4. A 60-GHz Adaptively Biased Power Amplifier with Predistortion Linearizer in 90-nm CMOS
5. A 65 nm CMOS Power Amplifier With Peak PAE above 18.9% From 57 to 66 GHz Using Synthesized Transformer-Based Matching Network
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 23-30 GHz 4-Path Series-Parallel-Combined Class-AB Power Amplifier with 23 dBm Psat, 38.5% Peak PAE and 1.3° AM-PM Distortion in 40nm Bulk CMOS;2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2023-06-11
2. A 60–64 GHz Power Amplifier for MM-Wave Radar Transceiver with 16.51-dBm Power and 23.34% PAE in 40-NM CMOS;2023 IEEE MTT-S International Wireless Symposium (IWS);2023-05-14
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