Author:
Bagamma B N,Patel K S Vasundara,Ravi Prasad
Cited by
3 articles.
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1. Energy Efficient Memory Decoder for SRAM Based AI Accelerator;2023 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS);2023-04-05
2. A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM;2021 IEEE 18th India Council International Conference (INDICON);2021-12-19
3. Design of High Speed and Power Efficient 16 × 8 SRAM Memory Using Improved 4 × 16 Decoder;Lecture Notes in Electrical Engineering;2021-09-10