End-to-End Industrial Study of Retiming
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8428827/8429321/08429367.pdf?arnumber=8429367
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-07
2. Logic Synthesis;FPGA EDA;2024
3. Trubol: Synthesis of Pipelined Circuits from Python-based DSL Specifications;2023 5th International Conference on Control Systems, Mathematical Modeling, Automation and Energy Efficiency (SUMMA);2023-11-08
4. Implementation of Retiming Technique for Clock Period Optimization by Brute-Force Approach;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07
5. Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops;IEEE Access;2023
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