Noise and Energy Consumption Analysis of SAR and SAR-Pipelined ADCs
Author:
Affiliation:
1. Fundación Fulgor,Córdoba,Argentina,5000
2. Universidad Nacional de Córdoba - CONICET,Laboratorio de Comunicaciones Digitales,Córdoba,Argentina,5000
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9762473/9762474/09762500.pdf?arnumber=9762500
Reference16 articles.
1. Input Referred Comparator Noise in SAR ADCs
2. A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS
3. A pipelined 5-Msample/s 9-bit analog-to-digital converter
4. A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique
5. Power consumption bounds for SAR ADCs
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1. A Noise Model Circuit Based On A High-Speed Pipeline ADC System;2023 9th International Conference on Computer and Communications (ICCC);2023-12-08
2. A Programmable Gain Dynamic Residue Amplifier in 65nm CMOS;2023 Argentine Conference on Electronics (CAE);2023-03-09
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