A 1.2 V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver

Author:

Boon C. C.,Krishna M. Vamshi,Do M. A.,Yeo K. S.,Do Aaron V.,Wong T. S.

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. S-Band Phase-Locked Loop Frequency Synthesizer for Satellite Communication and Space Applications;2024 IEEE/MTT-S International Microwave Symposium - IMS 2024;2024-06-16

2. A Low Mismatch Current Steering Charge Pump for High-Speed PLL;Proceedings of Second International Conference on Computational Electronics for Wireless Communications;2023

3. A 1.6GHz Ultra-Low Phase Noise GaAs HBT PLL for Anti-Radiation Applications;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

4. Linear CMOS $LC$ -VCO Based on Triple-Coupled Inductors and Its Application to 40-GHz Phase-Locked Loop;IEEE Transactions on Microwave Theory and Techniques;2017-08

5. A review of wireless-photonic systems: Design methodologies and topologies, constraints, challenges, and innovations in electronics and photonics;Optics Communications;2016-08

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