An Energy-Efficient Conditional-Boosting Flip-Flop with Conditional Pulse for Low Power Application-Reference-Cited by-同舟云学术

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An Energy-Efficient Conditional-Boosting Flip-Flop with Conditional Pulse for Low Power Application

Published:2022-10-07 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)
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Author:

Patidar Dipali¹,Mishra Alok Kumar¹,Vaithiyanathan Dhandapani¹,Kaur Baljit¹

Affiliation:

1. National Institute of Technology Delhi,Department of Electronics and Communication Engineering,Delhi,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9971791/9971808/09972127.pdf?arnumber=9972127

Reference20 articles.

1. 1.5V CMOS And BiCMOS Bootstrapped Dynamic Logic Circuits Suitable For Low-voltage VLSI

2. Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

3. Low Power High Speed 15-Transistor Static True Single Phase Flip Flop

4. A Static Contention-Free Differential Flip-Flop in 28nm for Low-Voltage, Low-Power Applications

5. A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Review of Dual-Edge Triggered Low-Power D Flip-Flops;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29

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