Design of Error Tolerant Subtractor using Truncation Approximation Technique
Author:
Affiliation:
1. National Institute of Technology,Dept. of ECE,Srinagar,India
2. Jamia Millia Islamia,Dept. of ECE,New Delhi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10127221/10127228/10127573.pdf?arnumber=10127573
Reference15 articles.
1. Approximate Multipliers Based on Inexact Adders for Energy Efficient Data Processing
2. Generalized low-error area-efficient fixed-width multipliers
3. On the Design of Approximate Restoring Dividers for Error-Tolerant Applications
4. Design of Approximate Subtractors and Dividers for Error Tolerant Image Processing Applications
5. Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing;zhu;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2009
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