Quantization Noise Suppression in Fractional-$N$ PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/6194305/06176273.pdf?arnumber=6176273
Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator;IEEE Access;2023
2. A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS;Electronics;2021-10-13
3. A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer;Microelectronics Journal;2021-10
4. A 0.045- to 2.5-GHz Frequency Synthesizer With TDC-Based AFC and Phase Switching Multi-Modulus Divider;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-12
5. A 7.1-GHz 0.7-mW Programmable Counter With Fast EOC Generation in 65-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-11
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