A CMOS Switched Load Harmonic Rejection Mixer for DTV Tuner Applications
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/6419840/06336803.pdf?arnumber=6336803
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09
2. A Direct-coupled Harmonic Rejection Mixer Employing IIP3 Improving Technology;2022 2nd International Conference on Computer Science, Electronic Information Engineering and Intelligent Control Technology (CEI);2022-09-23
3. Achieving high linearity and conversion gain in double balanced mixer with cascoded RF and LO stage;Analog Integrated Circuits and Signal Processing;2021-01-02
4. Improving HRR in 3P–8P harmonic rejection mixer using modified input transconductance stage in hard switching mixer;Analog Integrated Circuits and Signal Processing;2017-02-15
5. Design of 12-phase, 2-stage Harmonic Rejection Mixer for TV Tuners;Radioengineering;2016-04-14
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