A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS-Reference-Cited by-同舟云学术

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A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

Published:2013-08 Issue:8 Volume:60 Page:2009-2017
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Plouchart J.-O.,Ferriss M.,Natarajan A. S.,Valdes-Garcia A.,Sadhu B.,Rylyakov A.,Parker B. D.,Beakes M.,Babakhani A.,Yaldiz S.,Pileggi L.,Harjani R.,Reynolds S.,Tierno J. A.,Friedman D.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/6567958/06541965.pdf?arnumber=6541965

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With g_m -Boosting Technique;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-10

2. A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-10

3. Design of a 24-30GHz Wide Tuning-Range VCO for 5G Millimeter Wave Communication;2019 International Conference on Microwave and Millimeter Wave Technology (ICMMT);2019-05

4. A 52-to-67 GHz dual-core push–push VCO in 40-nm CMOS;International Journal of Microwave and Wireless Technologies;2018-02-12

5. Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits;IEEE Design & Test;2014-12

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