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Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors

  • Published:2018-12 Issue:12 Volume:65 Page:4285-4298
  • ISSN:1549-8328
  • Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
  • language:
  • Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Kim SungORCID,Howe Patrick,Moreau Thierry,Alaghi ArminORCID,Ceze LuisORCID,Sathe Visvesh S.

Funder

National Science Foundation

C-FAR, one of the six SRC STARnet Centers through MARCO and DARPA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

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3. RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

4. RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

5. AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-09
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