A 0.18-$\mu$m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/6419840/06327620.pdf?arnumber=6327620
Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 125 μ m-Pitch-Matched Transceiver ASIC With Micro-Beamforming ADC and Multi-Level Signaling for 3-D Transfontanelle Ultrasonography;IEEE Journal of Solid-State Circuits;2024-08
2. WITHDRAWN: A 32-channels analog multiplexer with crosstalk compensation technique in 45nm CMOS;Microelectronics Journal;2024-04
3. Sign-Sign LMS-Based Adaptive DFE for 4PAM Multi-Gbps Serial Links;2023 IEEE 13th Annual Computing and Communication Workshop and Conference (CCWC);2023-03-08
4. A Novel PWAM Signaling Scheme for High-speed Serial Interface;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2022-10-31
5. High-speed Serial Interface using PWAM Signaling Scheme;2022 19th International SoC Design Conference (ISOCC);2022-10-19
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