Area-Power Efficient Modulo $2^{n}-1$ and Modulo $2^{n}+1$ Multipliers for $\{2^{n}-1, 2^{n}, 2^{n}+1\}$ Based RNS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/6313475/06157663.pdf?arnumber=6157663
Cited by 35 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array;Electronics;2024-01-10
2. Efficient Configurable Modular Multiplier For RNS;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20
3. FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme;Applied Sciences;2023-09-18
4. Design of reverse converters for the general RNS 3-moduli set {2k, 2n − 1, 2n + 1};EURASIP Journal on Advances in Signal Processing;2023-09-04
5. A Parallel Prefix Modulo-(2 q + 2 q−1 + 1) Adder via Diminished-1 Representation of Residues;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08
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