Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits-Reference-Cited by-同舟云学术

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Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits

Published:2015-06 Issue:6 Volume:62 Page:1463-1471
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Verbeke Marijn,Rombouts Pieter,Vyncke Arno,Torfs Guy

Funder

Agency for Innovation by Science and Technology in Flanders (IWT)

EU FP7 DISCUS Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7112573/07103373.pdf?arnumber=7103373

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Backstepping Control Collaborative Shaft Torque Observer for Limit Cycle Oscillation Suppression of Fully Closed-Loop Gear Transmission Servo System;IEEE Transactions on Power Electronics;2024

2. A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-02

3. The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-01

4. A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop;IEICE Electronics Express;2020-10-25

5. A New Anti-Windup Compensator Based on Quantitative Feedback Theory for an Uncertain Linear System with Input Saturation;Applied Sciences;2019-07-24

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