Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits-Reference-Cited by-同舟云学术

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Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

Published:2019-04 Issue: Volume: Page:
ISSN:
Container-title:2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI)
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Author:

Kumar Ch. Narasimha,Madhumitha A.,Preetam N. Sesi,Gupta P. Vamsi,Anita J.P.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8851338/8862508/08862751.pdf?arnumber=8862751

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Research on Optimization Algorithm for Boundary Scan Interconnection Test Vector;2024 IEEE 7th International Electrical and Energy Conference (CIEEC);2024-05-10

2. Test Pattern Reduction Using Various ML Algorithms;2023 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER);2023-10-13

3. Design of Low Switching Pattern Generator for BIST Architecture;Micro-Electronics and Telecommunication Engineering;2022

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