Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology-Reference-Cited by-同舟云学术

Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology

Published:2022-12-03 Issue: Volume: Page:
ISSN:
Container-title:2022 International Electron Devices Meeting (IEDM)
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Author:

Qiao S.¹,Moran S.¹,Srinivas D.¹,Pamarti S.¹,Iyer S. S.¹

Affiliation:

1. University of California,Center for Heterogeneous Integration and Performance Scaling, Samuli School of Engineering,Electrical and Computer Engineering Department,Los Angeles (UCLA),CA,USA,90095

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019527.pdf?arnumber=10019527

Reference10 articles.

1. SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge

2. A 40-nm MLCRRAM Compute-in-Memory Macro With Sparsity Control, On-Chip WriteVerify, and Temperature-Independent ADC;li;IEEE JSSC,2022

3. The Impact of Self-Heating on Charge Trapping in High- $k$ -Metal-Gate nFETs

4. An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process

5. HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

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